Caspia Technologies GenAI for Semiconductor Cybersecurity is a pre-silicon security verification suite designed for System-on-Chip (SoC) designs. The solution addresses security risks in semiconductor hardware, including information leakage, access control violations, and vulnerabilities from third-party IP cores. The platform applies Generative AI to automate security verification tasks across the SoC development flow. It provides capabilities for automated design analysis, security asset identification, threat modeling, and security testbench generation. The solution supports static analysis, formal verification, and dynamic verification through emulation. SVx is a component of the suite that automates security property generation for formal verification. It generates natural language properties and corresponding SystemVerilog assertions that can be fed to formal verification tools. The tool functions as a sidecar to existing formal verification tools rather than replacing them. The platform aims to enable secure-by-design principles in semiconductor development by reducing manual security review requirements and addressing scalability challenges in traditional verification methodologies. It is designed to work alongside industry-standard logical verification flows for integration into existing development processes.